SI5330B-B00204-GM

The SI5330B-B00204-GM is a low-jitter low-skew Fanout Buffer optimized for high-performance PCB clock distribution applications. The device produces four differential or eight single-ended, low-jitter output clocks from a single input clock. The input can accept either a single-ended or a differential clock allowing the device to function as a clock level translator. It supports single-ended output formats of CMOS, SSTL and HSTL and differential formats of LVDS, LVPECL and HCSL. It is normally required that the LVDS driver be DC-coupled to the 100Ω termination at the receiver end. If your application requires an accoupled 100Ω load, contact the applications team for advice. It can accept single-ended and differential input clocks.

• Supports single-ended or differential input clock signals
• Generates four differential (LVPECL, LVDS, HCSL) or eight single-ended (CMOS, SSTL, HSTL) output
• Provides signal level translation
• Loss of signal (LOS) indicator allows system clock monitoring
• Output enable (OEB) pin allows glitchless control of output clocks
• 100ps Output-output skew
• 150fs RMS typical additive jitter

Applications

Communications & Networking, Fibre Optics, Clock & Timing