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CD74HC573M96 .

Latch, HC Family, 74HC573, D Type Transparent, Tri State, 30 ns, 7.8 mA, SOIC

CD74HC573M96 . - Latch, HC Family, 74HC573, D Type Transparent, Tri State, 30 ns, 7.8 mA, SOIC

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CD74HC573M96 .
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Latch, HC Family, 74HC573, Transparent, Tri State Non Inverted, 14 ns, 7.8 mA, SOIC

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Latch, HC Family, 74HC573, D Type Transparent, Tri State, 14 ns, 35 mA, SOIC

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Product Overview

The CD74HC573M96 is an octal CMOS Transparent D Latch with 3-state outputs. This high speed latch is designed for 2 to 6V VCC operation. When the LE input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered OE\ input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pull-up components. OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pull-up resistor.
  • Balanced propagation delays and transition times
  • Bus driver outputs drive up to 15 LS-TTL loads
  • Significant power reduction compared to LS-TTL logic ICs
  • Green product and no Sb/Br


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D Type Transparent

Tri State














MSL 1 - Unlimited
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